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dg884 vishay siliconix document number: 70071 s-52433erev. f, 06-sep-99 www.vishay.com faxback 408-970-5600 5-1 8 x 4 wideband video crosspoint array routes any input to any output wide bandwidth: 300 mhz low crosstalk: 85 db @ 5 mhz double buffered ttl-compatible latches with readback low r ds(on) : 45 optional negative supply reduced board space improved system bandwidth improved channel off-isolation simplified logic interfacing allows bipolar signal swings reduced insertion loss high reliability wideband signal routing and multiplexing high-end video systems ntsc, pal, secam switchers digital video routing ate systems the dg884 contains a matrix of 32 t-switches configured in an 8 4 crosspoint array. any of the in/out pins may be used as an input or output. any of the in pins may be switched to any or simultaneously to all out pins. the dg884 is built on a proprietary d/cmos process that combines low capacitance switching dmos fets with low power cmos control logic and drivers. the ground lines between adjacent signal input pins help to reduce crosstalk. the low on-resistance and low on-capacitance of the dg884 make it ideal for video and wideband signal routing. control data is loaded individually into four next event latches. when all next event latches have been programmed, data is transferred into the current event latches via a salvo command. current event latch data readback is available to poll array status. output disable capabilities make it possible to parallel multiple dg884s to form larger switch arrays. dis outputs provide control signals used to place external buffers in a power saving mode. for additional information see applications note an504 (faxback document number 70610).

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in 2 dgnd gnd v l in 3 rs gnd salvo in 4 wr gnd a 3 in 5 a 2 gnd a 1 in 6 a 0 gnd cs in 7 i /o plcc and clcc 6 5 4 3 2 1 44 43 42 41 40 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 top view gnd gnd in 8 gnd gnd gnd v out 1 gnd 2 out 3 gnd 4 out v+ gnd 0 out 1 1 1 2 3 4 in dis dis dis dis b b dg884 vishay siliconix www.vishay.com faxback 408-970-5600 5-2 document number: 70071 s-52433erev. f, 06-sep-99

temp range package part number 40 to 85 c 44-pin plcc dg884dn 55 to 125 c 44-pin clcc dg884am/883
rs i /o cs wr salvo actions 1 0 1 1 no change to next event latches 1 0 0 1 next event latches loaded as defined in table below 1 0 0 0 1 next event latches are transparent. 1 0 0 1 next event data latched-in 1 0 x 1 data in all next event latches is simultaneously loaded into the current event latches, i.e., all new crosspoint addresses change simultaneously when salvo goes low. 1 0 0 x 0 current event latches are transparent 1 0 x 1 current event data latched-in 1 0 0 0 0 both next and current event latches are transparent 1 1 1 1 1 a 0 , a 1 , a 2 , a 3 high impedance 1 1 0 1 1 a 0 , a 1 , a 2 , a 3 become outputs and reflect the contents of the current event latches. b 0, b 1 determine which current event latches are being read 0 x x 1 1 all crosspoints opened (but data in next event latches is preserved) all other states are not recommended.
dg884 vishay siliconix document number: 70071 s-52433erev. f, 06-sep-99 www.vishay.com faxback 408-970-5600 5-3 wr b 1 b 0 a 3 a 2 a 1 a 0 next event latches 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 in 1 to out 1 loaded in 2 to out 1 loaded in 3 to out 1 loaded in 4 to out 1 loaded in 5 to out 1 loaded in 6 to out 1 loaded in 7 to out 1 loaded in 8 to out 1 loaded 0 x x x turn off out 1 loaded 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 in 1 to out 2 loaded in 2 to out 2 loaded in 3 to out 2 loaded in 4 to out 2 loaded in 5 to out 2 loaded in 6 to out 2 loaded in 7 to out 2 loaded in 8 to out 2 loaded 0 x x x turn off out 2 loaded 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 in 1 to out 3 loaded in 2 to out 3 loaded in 3 to out 3 loaded in 4 to out 3 loaded in 5 to out 3 loaded in 6 to out 3 loaded in 7 to out 3 loaded in 8 to out 3 loaded 0 x x x turn off out 3 loaded 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 in 1 to out 4 loaded in 2 to out 4 loaded in 3 to out 4 loaded in 4 to out 4 loaded in 5 to out 4 loaded in 6 to out 4 loaded in 7 to out 4 loaded in 8 to out 4 loaded 0 x x x turn off out 4 loaded note: when wr = 0 next event latches are transparent. each crosspoint is addressed individually, e.g., to connect in 1 to out 1 thru out 4 requires a 0 , a 1 , a 2 = 0 to be latched with each combination of b 0 , b 1 . when rs = 0, all four dis outputs pull low simultaneously.
v+ to gnd 0.3 v to 21 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v+ to v 0.3 v to 21 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v to gnd 10 v to 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v l to gnd 0 v to (v+) + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs (v) 0.3 v to (v l ) + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first v s , v d (v) 0.3 v to (v) + 14 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 20 ma, whichever occurs first current (any terminal) continuous 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . current (s or d) pulsed 1 ms 10% duty 40 ma . . . . . . . . . . . . . . . . . . . . . . storage temperature (a suffix) 65 to 150 c . . . . . . . . . . . . . . . . . . . (d suffix) 65 to 125 c . . . . . . . . . . . . . . . . . . . operating temperature (a suffix) 55 to 125 c . . . . . . . . . . . . . . . . . . . (d suffix) 40 to 85 c . . . . . . . . . . . . . . . . . . . . power dissipation (package) a 44-pin quad j lead plcc b 450 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-pin quad j lead hermetic clcc c 1200 mw . . . . . . . . . . . . . . . . . . . . . . . . notes: a. all leads soldered or welded to pc board. b. derate 6 mw/ c above 75 c. c. derate 16 mw/ c above 75 c.
dg884 vishay siliconix www.vishay.com faxback 408-970-5600 5-4 document number: 70071 s-52433erev. f, 06-sep-99
test conditions unless specified a suffix 55 to 125 c d suffix 40 to 85 c parameter symbol v+ = 15 v, v = 3 v v l = 5 v, rs = 2.0 v salvo , cs , wr , i /o = 0.8 v temp b typ c min d max d min d max d unit analog switch analog signal range e v analog v = 5 v full 5 8 5 8 v drain-source on-resistance r ds(on) i s = 10 ma, v d = 0 v v aih = 2.0 v , v ail = 0.8 v room full 45 90 120 90 120 resistance match between channels r ds(on) v aih = 2 . 0 v , v ail = 0 . 8 v sequence each switch on room 3 9 9 source off leakage current i s(off) v s = 8 v, v d = 0 v, rs = 0.8 v room full 20 200 20 200 20 200 20 200 a drain off leakage current i d(off) v s = 0 v, v d = 8 v, rs = 0.8 v room full 20 200 20 200 20 200 20 200 na total switch on leakage current i d(on) v s = v d = 8 v room full 20 2000 20 2000 20 200 20 200 digital input/output input voltage high v aih full 2 2 v input voltage low v ail full 0.8 0.8 v address input current i ai v ai = 0 v or 2 v or 5 v room full 0.1 1 10 1 10 1 10 1 10 a address output current i ao v ao = 2.7 v, see truth table room 600 200 200 a address output current v ao = 0.4 v, see truth table room 1500 500 500 dis pin sink current i dis room 1.5 ma dynamic characteristics on state input capacitance e c s(on) 1 in to 1 out, see figure 11 room 30 40 f on state input capacitance e c s(on) 1 in to 4 out, see figure 11 room 120 160 f off state input capacitance e c s(off) sfi 11 room 8 20 20 pf off state output capacitance e c d(off) see figure 11 room 10 20 20 transition time t trans see figure 5 room 300 break-before-make interval t open see figure 5 full 10 10 salvo , wr turn on time t on r l = 1 k , c l = 35 pf 50% control to 90% output room full 300 500 300 ns salvo , wr turn off time t off 50% control to 90% output see figure 3 room full 175 300 175 charge injection q see figure 6 room 100 pc matrix disabled crosstalk x talk(dis) r in = r l = 75 f = 5 mhz, see figure 10 room 82 db adjacent input crosstalk x talk ( ai) r in = 10 , r l = 10 k f = 5 mhz, see figure 9 room 85 db all hostile crosstalk x talk(ah) r in = 10 , r l = 10 k f = 5 mhz, see figure 8 room 66 bandwidth bw r l = 50 , see figure 7 room 300 mhz
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test conditions unless specified a suffix 55 to 125 c d suffix 40 to 85 c parameter symbol v+ = 15 v, v = 3 v v l = 5 v, rs = 2.0 v salvo , cs , wr , i /o = 0.8 v temp b typ c min d max d min d max d unit power supplies positive supply current i+ all i a gnd 2 v room full 1.5 3 6 3 6 ma negative supply current i all inputs at gnd or 2 v rs = 2 v room full 1.5 3 5 3 5 ma digital gnd supply current i dg full 275 750 750 a logic supply current i l full 200 500 500 a functional operating supply volt v+ to v see o p eratin g v olta g e ran g e full 13 20 13 20 v functional operating supply volt- age range e v to gnd see operating v oltage range (typical characteristics) page 5 - 6 full 5.5 0 5.5 0 v age range v+ to gnd page 5 - 6 full 10 20 10 20 minimum input timing requirements address write time t aw sfi 1 full 20 50 50 minimum wr pulse width t wp sfi 1 full 50 100 100 write address time t wa sfi 1 full 10 10 10 chip select write time t cw sfi 1 full 50 100 100 write chip select time t wc sfi 1 full 25 75 75 minimum salvo pulse width t sp sfi 1 full 50 100 100 salvo write time t sw see figure 1 full 10 10 10 ns write salvo time t ws g room 20 50 input output time t io room 150 200 200 address output time t ao room 150 200 200 chip select output time t co room 150 200 200 chip select address time t ca room 60 100 reset to salvo t rs full 50 50 i /o address input time t ia room 50 notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. guaranteed by design, not subject to production test.
dg884 vishay siliconix www.vishay.com faxback 408-970-5600 5-6 document number: 70071 s-52433erev. f, 06-sep-99
adjacent input crosstalk all hostile crosstalk matrix disabled crosstalk f frequency (mhz) f frequency (mhz) f frequency (mhz) (db) talk(ai) x (db) talk(ah) x (db) talk(dis) x operating voltage area v negative supply (v) v+ positive supply (v) 1 10 100 100 80 0 60 40 20 1 10 100 120 100 20 80 60 40 1 10 100 120 100 20 80 60 40 21 19 17 15 13 11 9 0 1 2 3 4 5 6 operating voltage area
dg884 vishay siliconix document number: 70071 s-52433erev. f, 06-sep-99 www.vishay.com faxback 408-970-5600 5-7 figure 1. input timing requirements t sw t aw presetting device a cs for device a cs for device b address b 0 b 1 address a 0 a 3 wr salvo rs i /o select output 1 presetting device b don't care don't care select output 2 output n select input select input input reset occuring at any time results in all current event latches being cleared t wa t wa t aw t wa t wp t sp t rs t cw t ca t ia t ws t aw t wc t sp t sw t cw t ws input figure 2. output timing requirements t ao t ao cs for device a cs for device b interrogating device a address b 0 b 1 address a 0 a 3 wr salvo rs i /o reset occuring at any time results in all current event latches being cleared t io select current event latch 1 select current event latch interrogating device b output t c o t ao latch n t ca out n t c o t c a t ao t ia address output 1 address output
symbol parameter description t aw address to write minimum time address must be valid before wr goes high t wa write to address minimum time address must remain valid after wr pulse goes high t wp wr pulse minimum time of wr pulse width to write address into next event latches t cw chip select to wr minimum time chip select must be valid before a wr pulse t wc wr to chip select minimum time chip select must remain valid after wr pulse t sp salvo pulse minimum time of salvo pulse width t ws wr to salvo minimum time from wr pulse to salvo to load new address t sw salvo to wr minimum time from salvo pulse to wr to load current address t ia i /o to address in minimum time i /o must be valid before address applied t rs rs to salvo minimum time rs must be valid before salvo pulse t io i /o to output minimum time i /o must be valid before address output valid t ao address to output minimum time address b x must be valid until address a x output valid t co cs to output minimum time cs must be valid until a x output is valid t ca cs to address in minimum time cs must be valid before address applied if i /o is high
dg884 vishay siliconix www.vishay.com faxback 408-970-5600 5-8 document number: 70071 s-52433erev. f, 06-sep-99 figure 3. salvo turn on/off time figure 4. wr turn on/off time 0 v 3 v 0 v 50% 90% 90% 50% 1 v 3 v t off t on a 0 , a 1 , a 2 salvo v o 0 v 3 v 0 v 50% 90% 90% 50% 1 v 3 v t off t on a 0 , a 1 , a 2 wr v o figure 5. transition time and break-before-make interval 0 v 50% 3 v 90% a 0 , a 1 , a 2 v o t trans t bbm 3 v 5 v 15 v v v+ gnd 35 pf 3 v 1 v dg884 1 k a 0 , a 1 , a 2 in 1 in 2 in 8 salvo b 0 b 1 i /o cs wr a 3 rs out 1 v o v l dgnd 3 v 5 v 15 v v v+ gnd 35 pf 3 v 1 v dg884 1 k a 0 , a 1 , a 2 in 1 wr b 0 b 1 i /o cs salvo a 3 rs out 1 v o v l dgnd 3 v 5 v 15 v v v+ gnd 3 v 1 v dg884 dgnd 1 k a 0 , a 1 , a 2 in 1 in 8 wr b 0 b 1 i /o cs salvo a 3 rs out 1 v o v l in 2 in 8 in 2 in 7
dg884 vishay siliconix document number: 70071 s-52433erev. f, 06-sep-99 www.vishay.com faxback 408-970-5600 5-9 figure 6. charge injection figure 7. 3 db bandwidth figure 8. all hostile crosstalk figure 9. adjacent input crosstalk figure 10. matrix disabled crosstalk figure 11. on-state and off-state capacitances 3 v 5 v 15 v v v+ gnd 5 v dg884 dgnd a 0 , a 1 , a 2 in 1 wr b 0 b 1 i /o cs salvo rs out 1 v o v l a 3 35 pf 3 v 5 v 15 v v v+ gnd dg884 dgnd in 8 wr b 0 b 1 i /o cs salvo rs out 1 v o v l 50 50 signal generator wr a 0 a 3 5 v a 3 v o q = v 0 c l v outputs inputs any one input to any one outputeall remaining inputs connected to remaining outputs r in 10 r l 10 k v o 10 k signal generator 75 v outputs all crosspoints open inputs r l 75 v o r in 10 signal generator 75 v n 1 v n v n + 1 r in 10 any input or output pin to adjacent input or output pin r l 10 k x talk(ah) 20 log 10 v out v x talk(dis) 20 log 10 v out v x talk(ai) 20 log 10 v n1 v n or 20 log 10 v n 1 v n signal generator 75 5 v 15 v 3 v dgnd dg884 v l in 2 in 3 in 4 in 5 in 6 in 7 gnd v v+ out 1 in 8 out 2 out 3 out 4 rs cs i/o a0o = off-state a1o = on-state meter hp4192a impedance analyzer or equivalent in 1
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pin symbol description 1, 3, 4, 6, 8, 10, 12, 14, 16, 18, 20, 41, 43 gnd analog signal ground 39 dgnd digital ground 26 v+ positive supply voltage 21 v negative supply voltage 38 v l logic supply voltageegenerally 5 v 5, 7, 9, 11, 13, 15, 17, 19 in 1 to in 8 8 analog input channels 2, 40, 42, 44 out 1 to out 4 4 analog output channels 29 i /o determines whether data is being written into the next event latches or read from the current event latches 30 cs chip selectea logic input 31, 32, 22, 24 a 0 , a 1 , a 2 , a 3 in addresselogic inputs or outputs as defined by i /o pin, select one of eight in channels 27, 28 b 0 , b 1 out addresselogic inputs, select one of four out channels 35 wr write command that latches a 0 , a 1 , a 2 , a 3 into the next event latches 36 salvo master write command, that in one action, transfers all the data from next event latches into current event latches 37 rs resetea low will clear the current event latches 22, 23, 24, 25 dis 1 to dis 4 open drain disable outputsethese outputs pull low when the corresponding out channel is off
the dg884 is the world's first monolithic wideband crosspoint array that operates from dc to >100 mhz. the dg884 offers the ability to route any one of eight input signals to any one of four out pins. any input can be routed to one, two, three or four outs simultaneously with no risk of shorting inputs together (guaranteed by design). each crosspoint is configured as a ato switch in which dmos fets are used due to their excellent low resistance and low capacitance characteristics. each out line has a series switch that minimizes capacitive loading when the out is off. interfacing the dg884 was designed to allow complex matrices to be developed while maintaining a simple control interface. the status of the i /o pin determines whether the dg884 is being written to or read from (see figures 1 and 2). in order to write to an individual latch, cs and i /o need to be low, while rs , wr and salvo must be high. the in to out path is selected by using address a 0 through a 3 to define the in line and address b 0 and b 1 to define the out line. that is, the in defined by a 0 through a 3 is electrically connected to the out defined by b 0 , b 1 . this chosen path is loaded into the next event latches when wr goes low and returns high again. this operation is repeated up to three more times if other crosspoint connections need to be changed. upon completing all crosspoint connections that are to be changed in a single device, other dg884s can be similarly preset by taking the cs pin low on the appropriate device. when all dg884s are preset, the current event latches are simultaneously changed by a single salvo command applied to all devices. in this manner the crosspoint configuration of any number of devices can be simultaneously updated. dis outputs four open drain disable outs are provided to control external line drivers or to provide visual or electrical signaling. for example, any or all of the dis outs can directly interface with a clc410 video amplifier to place it into a high impedance, low-power standby mode when the corresponding out is not being used. (see figure 15). the dis outputs are low and sink to v when corresponding out is open or rs is low. reset the reset function (rs ) allows the resetting of all crosspoints to a known state (open). at power up, the reset facility may be used to guarantee that all switches are open. it should be noted that rs clears the current event latches, but the next event latches remain unchanged. this useful facility allows the user to return the matrix to its previous state (prior to reset) by simply applying the salvo command. alternatively, the user can reprogram the next event latches, and then apply the salvo command to reconfigure the matrix to a new state.
dg884 vishay siliconix document number: 70071 s-52433erev. f, 06-sep-99 www.vishay.com faxback 408-970-5600 5-11
readback the i /o facility enables the user to write data to the next event latches or to read the contents of the current event latches. this feature permits the central controller to periodically monitor the state of the matrix. if a power loss to the controller occurs, the readback feature helps the matrix to recover rapidly. it also offers a means to perform pc board diagnostics both in production and in system operation. / mux 3 decoder 4 / 4 q 0 q 3 next event latch 3 / 7 current event latch 3 data buffers / 4 cmos output buffers / 9 8 8 analog inputs mux 1 out 1 8 t-switches 1 series switch 8 mux 2 out 2 8 out 3 mux 4 out 4 en en dis 3 open drain output a 0 a 1 a 2 a 3 cs wr salvo i /o b 0 b 1 rs one of four blocks of logic/latches shown figure 12. control circuitry decoders/ drivers
wr salvo in 1 in 2 in 8 dg884 b 0 b 1 a 0 a 1 a 2 a 3 reset rs dis 1 out 1 twoesi584 quad unity-gain buffers clc410 75 75 figure 13. fully buffered 8 x 4 crosspoint note: dis outputs are used to power down the si582 amplifiers. x2 dis 2 out 2 x2 dis 3 out 3 x2 dis 4 out 4 x2 x1 x1 x1
dg884 vishay siliconix www.vishay.com faxback 408-970-5600 5-12 document number: 70071 s-52433erev. f, 06-sep-99 dg884 +5 v +15 v 3 v + ++ v v+ c 2 c 1 c 1 c 2 51 51 51 c 1 c 2 c 1 = 1 f tantalum c 2 = 100 nf ceramic v l figure 14. dg884 power supply decoupling 6 5 4 3 2 1 0 024681012141618 logic threshold (v) v th v l logic supply (v) figure 15. switching threshold voltage vs. v l power supplies and decoupling a useful feature of the dg884 is its power supply flexibility. it can be operated from dual supplies, or a single positive supply (v connected to 0 v) if required. allowable operating voltage ranges are shown in operating voltage range (typical characteristics) graph, page 5-6. note that the analog signal must not go below v by more than 0.3 v (see absolute maximum ratings). however, the addition of a v pin has a number of advantages: 1) it allows flexibility in analog signal handling, i.e. with v = 5 v and v+ = 15 v, up to 5-v ac signals can be accepted. 2) the value of on-capacitance [c s(on) ] may be reduced by increasing the value of v. it is useful to note that optimum video differential phase and gain occur when v is 3 v. note that v+ has no effect on c s(on) . 3) v eliminates the need to bias an ac analog signal using potential dividers and large decoupling capacitors. it is established rf design practice to incorporate sufficient bypass capacitors in the circuit to decouple the power supplies to all active devices in the circuit. the dynamic performance of the dg884 is adversely affected by poor decoupling of power supply pins. also, since the substrate of the device is connected to the negative supply, proper decoupling of this pin is essential. rules: 1) decoupling capacitors should be incorporated on all power supply pins (v+, v, v l ). 2) they should be mounted as close as possible to the device pins. 3) capacitors should have good high frequency charac- teristicsetantalum bead and/or monolithic ceramic disc types are suitable. recommended decoupling capacitors are 1- to 10- f tantalum bead, in parallel with 100-nf monolithic ceramic. 4) additional high frequency protection may be provided by 51- carbon film resistors connected in series with the power supply pins (see figure 14). the v l pin permits interface to various logic types. the device is primarily designed to be ttl or cmos logic compatible with +5 v applied to v l . the actual logic threshold can be raised simply by increasing v l .
dg884 vishay siliconix document number: 70071 s-52433erev. f, 06-sep-99 www.vishay.com faxback 408-970-5600 5-13 a typical switching threshold versus v l is shown in figure 15. these devices feature an address readback facility whereby the last address written to the device may be read by the system. this allows improved status monitoring and hand shaking without additional external components. when the i /o assigns the address output condition, the a x address pins can sink or source current for logic low and high, respectively. note that v l is the logic high output condition. this point must be respected if v l is varied for input logic threshold shifting. note: even though these devices are designed to be latchup resistant, v l must not exceed v+ by more than 0.3 v in operation or during power supply on/off sequencing. layout the plcc package pinout is optimized so that large crosspoint arrays can be easily implemented with a minimum number of pcb layers (see figure 16). crosstalk is minimized and off-isolation is optimized by having ground pins located adjacent to each input and output signal pins. optimum off-isolation and low crosstalk performance can only be achieved by the proper use of rf layout techniques: avoid sockets, use ground planes, avoid ground loops, bypass the power supplies with high frequency type capacitors (low esr, low esl), use striplines to maintain transmission line impedance matching. video in bus video in bus video in bus video in bus video out bus video out bus video out bus video out bus address bus address bus figure 16. 16 x 8 expandable crosspoint matrix using dg884

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